(1) Field of the Invention
The present invention relates to semiconductor devices and more particularly to a method of forming buried source line in memory cells in order to reduce the size of integrated circuits.
(2) Description of the Related Art
The technological advances in the semiconductor industry are directed towards improvements in performance, that is speed, and productivity, that is, less unitary cost. By the nature of the semiconductor physics and technology, and fortunately so, the improvements in one feed the other. Thus, reduction in the size of the elements in integrated circuits increase the packing density of elements which in turn help reduce the size of the chip in which the circuits reside. Alternatively, more circuits can be packed in the same area chip, which together help improve productivity in semiconductor manufacturing. At the same time, as the circuits are packed closer together, signal propagation, that is, communication through shorter distances between circuits becomes faster, and, therefore, the overall performance is greatly improved.
When silicon-gate technology was developed, a means had to be provided for making contact between the polysilicon layer and the single-crystal substrate. In early silicon-MOS circuits, such contacts were made by using either a metal link to interconnect the polysilicon and the substrate as shown in prior art FIG. 1a, or by the so-called butted contacts as shown in FIG. 1b. In FIG. 1a, the metal link (60), usually aluminum, is formed over a substrate (10) having a polysilicon layer (40) separated from the substrate and the metal layer by means of first and second dielectric silicon oxide layers (30) and (50), respectively, thus providing the contact between the polysilicon layer and the substrate.
With the butted contact, polysilicon (poly) is aligned with the active-device area (20) to which the contact will be established. This is done by patterning the polysilicon film after it has been deposited. After insulating layer (30) has been deposited to cover the poly, a contact window that overlaps both the poly and the substrate is opened, exposing both poly layer (40) and substrate (10). Metal is deposited to fill the contact, thereby electrically linking the two regions together (FIG. 1b). The butted contact conserves area by eliminating the space required between the separate contact windows when the approach of FIG. 1a is used.
The butted contact of FIG. 1b was later replaced by buried contact shown in FIG. 1c, because more area is conserved as shown in the same Figure. With the buried contact, direct contact is made between polysilicon and the substrate, eliminating the need for a metal link to form the contact over region (20). In this structure, a window is opened in the first dielectric layer (30), which is now a thin gate oxide, over the substrate area (20) at which the contact is to be made. When the polysilicon is subsequently deposited, it is in direct contact with the substrate in these opening but is isolated from the substrate by the gate and field oxides everywhere else (not shown). As it will be known by those skilled in the art, an ohmic contact is formed at the ploy-substrate Si interface by the diffusion into the substrate of dopant present in the polysilicon. A second dielectric (50) is then deposited to cover the contact as shown in FIG. 1c. The structure is called a "buried contact" because a metal layer can cross over the area of the substrate where a contact has been established without making an electrical connection to it. As will be apparent from the structure, therefore, the use of buried contacts in silicon-gate technology proves an important benefit in that it makes available an additional level of interconnect on the integrated circuit.
As memory and logic devices are scaled down in size by taking advantage of buried elements such as buried source and drain regions with smaller line widths and pitches, newer challenges arise. For example, as line pitches decrease, the buried line sheet resistance increases. Moreover, as the line sheet resistance increase, memory and logic circuit performance decrease. These relationships present the process designer with a trade off problem between smaller buried conductive regions and better circuit performance.
Smaller buried conductive regions create other process related problems, as described in U.S. Pat. No. 5,382,534. Buried conductive lines are designed with higher impurity concentrations to lower the line resistivity. During oxidation processes, the highly doped line areas oxidize at a higher rate than the lower doped surrounding areas. This enhanced oxidation rate is a function of the doping level of the highly doped line areas, but with the usual doping levels, the doped areas oxidize about four times as fast as the undoped areas. This enhanced oxidation creates surface topology steps between the non-doped device areas and the doped line area. The surface topology can cause yield problems in subsequent layers. The topology can cause photolithography depth of field and focusing problems.
Sheu, et al in U.S. Pat. No. 5,382,534 disclose a method for forming buried conductive regions in a trench that provides a smooth surface topology, smaller devices and improved device performance. The buried regions have two conductive regions, the first on the trench sidewalls, the second at the bottom of the trench. In addition, two buried layers are formed between adjacent buried conductive regions: a threshold voltage layer near the substrate surface and an anti-punchthrough layer formed at approximately the same depth as the conductive regions on the trench bottoms. The first conductive region and the anti-punchthrough layer have the effect of increasing the punchthrough voltage without increasing the threshold voltage. The first and second regions also lowers the resistivity of the buried regions, according to Sheu, et al, allowing the use of smaller line pitches and therefore smaller devices.
Wen, et al, in U.S. Pat. No. 5,602,049 disclose a method of fabricating a buried structure SRAM cell having ultra-high density. Here, higher packing density is made possible by eliminating the field oxide and hence bird's beak encroachment between active regions.
Richardson, on the other hand, discloses in U.S. Pat. No. 5,017,977 dual EPROM cells formed on the walls of a trench etched deep into a substrate. The trenches are then filled with doped polycrystalline semiconductor material. The doping of this semiconductor material diffuses into the silicon substrate during subsequent processing steps. This diffusion forms the drain of the floating gate field effect transistor. Then, by etching back the polysilicon and the silicon dioxide on the sidewalls, defining the conductive line at the bottom of the trench, growing gate oxide on the sides of the trench, depositing a second polysilicon layer and etching the same to provide polysilicon sidewalls, growing an interlevel dielectric, depositing another layer of polysilicon on the surface of the substrate to form gate lines of the cell, etching the latter polysilicon layer to remove the areas between the formed word lines, and further etching to remove interlevel dielectric and floating gate polysilicon between the EEPROM cells, vertical floating gate field effect transistors are fabricated on either side of a trench, bit lines are formed between and at the bottom of trenches which are perpendicular to the word lines over the trenches.
Another vertical channel device having buried source is described by Hsu in U.S. Pat. No. 5,627,393. In this approach, two levels of trenches are formed. The lower level trenches are etched through a well region into the buried source region and then filled with polysilicon to form gate electrodes. Drain regions are formed adjacent to the trenches by depositing, and etching back a second polysilicon layer and then ion implanting to form drain regions. Two sets of contact upper trenches are formed through silicon oxide layers subsequently deposited. The contact trenches are filled with tungsten to establish contact with drain and source regions.
Still another type of vertical memory cell array is disclosed by Mori in U.S. Pat. No. 5,576,567 using a vertical floating that can be fabricated with reduced cell areas and channel length. The array can be made contactless, half-contact or full contact, trading speed for increased cell area. A still different vertical channel device having buried source is shown by Hsu in U.S. Pat. No. 5,627,393.
The present invention discloses a different method of fabricating a semiconductor device, in particular, a memory cell, having both the source region and the source line buried within the substrate. The source line is formed in a trench in a substrate over the source region. This provides the attendant advantages of extended sidewall area, smaller sheet resistance, punch-through protection and yet smaller cell area, therefore, smaller chip size, and faster access time as claimed in the embodiments of this invention. The buried source disclosed here is integrated with source line which is also buried within the substrate.